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AD9985A
Table 16. Active Hsync Override Settings
Table 21. Clamp Input Signal Source Settings
Override
0
1
Result
Autodetermines the active interface (power-up
default)
Override, Bit 3 determines the active interface
Clamp Function
0
1
Result
Internally generated clamp signal (power-
up default)
Externally provided clamp signal
0E
3 Active Hsync Select
A 0 enables the clamp timing circuitry controlled by
This bit is used under two conditions. It is used to
select the active Hsync when the override bit is set
(Bit 4). Alternately, it is used to determine the active
Hsync when not overriding, but both Hsyncs are
detected.
Table 17. Active Hsync Select Settings
clamp placement and clamp duration. The clamp
position and duration is counted from the leading
edge of Hsync.
A 1 enables the external CLAMP input pin. The three
channels are clamped when the clamp signal is active.
The polarity of clamp is determined by the clamp
Select
0
Result
Hsync input (power-up default)
polarity bit (Register 0x0F, Bit 6).
1
0E
Sync-on-green input
2 Vsync Output Invert
This bit inverts the polarity of the Vsync output
0F
6 Clamp Input Signal Polarity
This bit determines the polarity of the externally
provided clamp signal.
Table 18 shows the effect of this option.
Table 22. Clamp Input Signal Polarity Settings
Table 18. Vsync Output Invert Settings
Invert Vsync Output
0 Invert (power-up default)
Clamp Function
1
0
Result
Active low (power-up default)
Active high
1
0E
No invert
1 Active Vsync Override
This bit is used to override the automatic Vsync
selection. To override, set this bit to Logic 1. When
overriding, the active interface is set via Bit 0 in this
register.
Logic 1 means that the circuit clamps when CLAMP is
low, and it passes the signal to the ADC when CLAMP
is high.
Logic 0 means that the circuit clamps when CLAMP is
high, and it passes the signal to the ADC when
CLAMP is low.
Table 19. Active Vsync Override Settings
Override Result
0 Autodetermines the active Vsync (power-up default)
1 Override, Bit 0 determines the active Vsync
0F
5 Coast Select
This bit is used to select the active Coast source. The
choices are the COAST input pin or Vsync. If Vsync is
selected, the additional decision to use the Vsync
0E
0 Active Vsync Select
This bit is used to select the active Vsync when the
override bit is set (Bit 1).
input pin or the output from the sync separator needs
to be made (Register 0x0E, Bits 1, 0).
Table 23. Power-Down Settings
Table 20. Active Vsync Select Settings
Power-Down
Result
Select
0
1
0F
Result
Vsync input (power-up default)
Sync separator output
7 Clamp Input Signal Source
This bit determines the source of clamp timing.
0
1
0F
COAST input pin
Vsync (See the Coast Select section)
4 Coast Input Polarity Override
This register is used to override the internal circuitry
that determines the polarity of the Coast signal going
into the PLL.
Rev. 0 | Page 22 of 32
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